Although Marcel's article in Vol 13 is very complete, some of the more practical desing information like FPGA code and PCB layouts didn't make it into the printed version. Marcel has graciously agreed to make the complete Tube Dac data package available here. This has everything needed for adventurous builders to replicate this design.
Update January 16, 2018: updated version 2.1 from previous version 2: following discussions at diyaudio.com, Marcel made some changes to his tube DAC. The zip file contains version 2.1 of the Verilog code and user constraints file for the valve DAC, as well as an MCS file that can be directly programmed into the flash memory of the FPGA module. Use the MCS file if you want to use the code as-is, the Verilog and UCF files are only needed for those who want to change the code themselves.
Compared to version 1, version 2.1 adds an I2S input on the extension connector. This input (which supports 2.8224 MHz DSD64 over DoP) can also be switched to a raw DSD mode, in which it supports 2.8224 MHz DSD64 and 5.6448 MHz DSD128. For PCM, the extra I2S input supports sample rates from 12.5 kHz up to 216 kHz and word lengths from 8 up to and including 32 bits. The I2S input can only operate in slave mode.
Compared to version 2, version 2.1 fixes a bug that could bring the DSD FIR filters into an undefined state.
For completeness' sake, this zip archive also contains the missing Gerber file for a backside legend layer for the main PCB, KiCadtop-B.SilkS.gbo. The original design data package had no backside legend because the Eurocircuits PCBproto process by default has no backside legend. However, the extra costs for adding a backside legend are only 0 euros, which is negligible compared to the total costs of the project. Besides, people may want to use other PCB manufacturers.
With one exception, the generated FIR filters and FIFOs used in version 2.1 of the valveDAC Verilog code are exactly the same as those used in version 1. See the documentation of version 1 to see how to generate them. (Again this is only relevant if you want to change something and, hence, can't use the MCS file.)
The exception is the filter type firdsd6 that is used at two places in module prefilter.v. These are generated by the Xilinx FIR compiler version 5.0 with exactly the same settings, coefficient file et cetera as the original firdsd filters (used in version 1 of the valveDAC Verilog code, see the documentation of version 1), except that the input word length is changed from 2 bits to 6 bits. (This automatically also results in a four bits longer output word length.)
The extra I2S input is mapped to these extension connector pins:
P9 pin 1: sel4192in, 0 selects the I2S (or raw DSD) input, 1 selects the DIX4192 S/PDIF interface. Debounced input with internal pull-up that can be connected to a fifth contact of the source selection switch.
P9 pin 3: mutei2sin, 1 mutes the sound when it comes from the I2S input.
P9 pin 5: datai2sin, I2S audio data input or raw DSD left audio data input.
P9 pin 7: deemni2sin, low level activates 50 us/15 us de-emphasis when the I2S input is active.
P9 pin 9: bcki2sin, bit clock for the I2S or raw DSD input.
P9 pin 11: lrcki2sin, word clock for the I2S input or right channel raw DSD data.
P9 pin 13: dsd64_128, must be 0 for DSD64 and 1 for DSD128 when the raw DSD interface is used.
P9 pin 15: dsdon, must be 0 for PCM or DoP, 1 for raw DSD.
P9 pins 2, 4, 6, 8, 10, 12, 14, 16: ground
P9 pins 17, 18, 19, 20: 3.3 V supply pins, see the schematic.
All inputs have internal pull-ups except dsdon and dsd64_128, which have internal pull-downs. The extension connector can be left unconnected when the I2S input isn't needed.
The logic high level is nominally 3.3 V. The logic high level can be reduced if needed by changing the power supply voltage of FPGA I/O bank 0. In principle the levels in the UCF file then have to be updated and everything has to be re-synthesized and re-implemented, but if you are lucky it might work without that.
A .zip with all modified files can be downloaded for free.