Welcome to my place!

Audio Resource Jan Didden

It's great to have you here!

This place is where I talk about my personal projects, interests and whatnot. Not necessarily related to audio, although it often is. Under the Musings button you'll find things related to perception and conciousness which of course are very much applicable to audio!

My library lists lots of (historic) audio papers and studies that I personally find important to understand many different issues in audio.

I also have collected the interviews I've done with audio luminaries. Take some time to read and digest them - there are very interesting and worthwhile gems in each of them! My projects however is audio stuff - things I designed, wrote articles about, and my personal system. Comments and remarks are always welcome!

Last but surely not least, let me mention my publication Linear Audio. Published twice per year, over 200 pages of technical audio related articles from international authors. Article abstracts and author bio's can be read at the website, and some articles are available for free online.

So, take a look around, explore the various areas and let me know what you think!

On Safe Operating Area issues

Thermal issues in MOSFETs operating in linear mode.

During the development of my electrostatic Direct Drive amplifier I ran into SOA issues with the 4.5kV high-voltage MOSFETs. Several people pointed me to pertinent papers on this subject, and I decided to post them here for whoever has the same issues.

The basic issue is with using (high voltage) MOSFETs developed for fast switching and low Rdson for a linear application. We have been told that MOSFETs do not have the secondary breakdown problems that Bipolars have. This is the phenomenon that due to irregularities in the BJT die, and the negative temperature coefficient, a small spot on the base-emitter junction might become a bit hotter than the surroundings, and will tend to conduct more current than the surroundings, thus gets even hotter, thus hogs even more current etc and the result is thermal runaway and ultimately destruction of the device. It happens primarily with simultaneous combinations of high Vce and high Ic even if the resulting power dissipation is lower than the maximum allowed.

Basically, MOSFETs being minority carrier devices do not exhibit this phenomenon and if you compare the Safe Operating Area graphs of a power BJT to a power MOSFET the difference is glaring. However (there always is an however) in a high voltage MOSFET, a small Id current combined with a (very) high Vds something similar can occur. In such a case the Vgs is just above the threshold value, opening up the MOSFET just a bit. The MOSFET die consists of many (100.000 or more) small 'cells' in parallel and they can have very small differences in threshold voltages. Normally this is no issue when you use them as switches because the Vgs is either very low if the MOSFET is off, or very high when the switch is maximally conducting. But when 'just open' the small differences in thresholds between different cells starts to cause differences in current in different cells, and what do you know, you get current hogging that runs away because the threshold voltage has a negative temperature coefficent. So the device may destruct and it just looks like second breakdown although the mechanism is different.

I got suspicious when reading the IXYS high voltage MOSFET data sheets which showed a very unusual SOA graph; see for instance http://ixapps.ixys.com/DataSheet/DS100498C(IXTH-T02N450HV).pdf. After some extended searching, and with help from my friend Ian Hegglun, I collected several papers detailing the issue:

The IXYS app note IXAN0068 ; Fairchilds' AN-4161 ; NASA's report NASA/TM-2010-216684 ;

The original study by Spirito et al on developing a Spice model that takes into account these phenomena.

Finally, I got in touch with Adrian Koh, Director, Business Development at NXP Semiconductor USA, who filled in the last blanks (for which I thank him):

'Let me share with you what happen inside the MOSFET during linear mode operation. There are hundred thousands of individual MOSFET cells connected in parallel on the Silicon. Hence, a larger piece of silicon has lower Resistance. Although they are "born" the same day, they do have subtle differences in individual electrical characteristic just like any identical twin kids having character of their own (unfortunately we live in an imperfect but interesting world). In MOSFET linear mode ops. you bias the gate just enough to open the channel for the electrons to flow. [snip]. Now this is just 1 cell. Multiply them by hundred thousands of those [snip]. Today's process controls are optimal. Depending on the test regime, sometime defects do get out into the market. Adam & myself have developed alot of tests to detect single cell defectivity. So we understood that these do exist. Sometime a rogue single cell having a significant difference in Vth (usually lower Vth) will result in hotspot as that single cell allows more current to flow than the others (i.e. higher power dissipation = more heat). If the overall thermal sink is efficient, it will provide sufficient cooling to prevent that hotspot going into thermal runaway. Sometime a cluster of cells having similar behaviour can quickly exacerbate the situation. Again if your cooling is sufficient, it is ok. If the hotspot is generating more heat than what your thermal budget can remove, it will go into thermal runaway resulting in catastrophic failure. So operating at lower current is not a guarantee safe ops in linear mode. For what I see your setup is fine. Just ensure sufficient cooling. So any hotspot form is contained.'




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